1. Field of the Invention
This invention relates to a semiconductor device to be used for an electronic circuit device, particularly to a thin film transistor having an SOI structure and a method for preparing the same.
2. Related Background Art
Thin film transistors have been recently attracting attention as semiconductor devices which constitute three-dimensional integrated circuits, contact type image sensors and devices for planar displays. Particularly in silicon thin film transistors, higher performances are effected by making crystallinity approximate to that of single crystal. Quite recently studies are going to be done in order to obtain the film thickness with a very high mobility of carrier by the mechanism inherent in an ultra-thin film (0.1 .mu.m or less). However, in such studies, only a specific characteristic is of interest, and how other transistor characteristics change accompanied therewith has not been clarified or even grasped.
The present inventors have pursued the study concerning the overall electrical characteristics of thin film transistors having SOI structures, and consequently found that the drain dielectric strength when the gate voltage is 0 volt (during OFF) is abruptly deteriorated, if the film thickness of the semiconductor film become thinner than a certain film thickness. The present inventors have made many experimentations repeatedly, and consequently found that the phenomenon as described below occurred. That is, while the avalanche breakdown at the drain edge which determines the drain dielectric strength is generated in the vicinity of the gate interface generally in the case of a thick film, it is generated in the vicinity of the interface with the subbing insulating substrate at a certain film thickness or less. More specifically, for example, in an SOI (Semiconductor on Insulator) type insulated gate field effect transistor constituted by formation of a thin film semiconductor layer, a gate insulating film and a gate electrode on a thick insulating substrate, it has been said in the prior art that the avalanche breakdown occurs initially in the vicinity of the gate interface because the maximum field is concentrated at the vicinity of the gate interface, and its tendency does not depend of the film thickness of the semiconductor layer. In contrast, the present inventors, on the basis of a new thought to consider the presence of an interface fixed charge (Qss) between the subbing insulating substrate and the semiconductor layer in the real SOI structure, first performed simulation. Then, as expected, although the electrical field was stronger on the gate interface side as compared with the vicinity of the subbing interface at a certain film thickness or less, the actual avalanche breakdown was found to take place in the vicinity of the subbing interface. Although a more detailed theoretical mechanism is now in the course of clarification, probably the avalanche breakdown depends not only on the electrical field, but also the number of carriers, and when Qss is accounted for at the gate and the vicinity of the subbing interface, this may be the cost of a greater influence of the subbing interface on the number of carriers.
To make the technique as described above easier to understand, first the SOI type field effect transistor of the prior art is described.
FIG. 1A shows a cross-sectional structure of the SOI type thin film field effect transistor of the prior art (A type). Also, FIG. 1B is a schematic sectional view showing the SOI type thin film field effect transistor to which an off-set structure is applied (B type). The distance of the off-set is prepared so as to be equal to the distance of the off-set in an embodiment of the present invention as described below. Here, 1 is an insulating substrate, 2 semiconductor layer, 3 a gate insulating layer, 4 gate electrode.
In the A type of the prior art type, dielectric strength is, for example, as low as 6 volts. On the other hand, when off-set as in the B type obtained by improvement thereof, even if another structure is the same, due to the influence of the electrical field near the gate interface being relaxed, the electrical field at the subbing interface is indirectly relaxed. As the result, the dielectric strength is more or less improved. However, its value is, for example, as low as 10 volts, and no practical value can be obtained. In a thin film field effect transistor, because it is a thin film, the region with the strongest electrical field depends on the position of junction between the drain and the channel on the gate insulating film side, and this region is in the vicinity of the vertical line from the junction position to the subbing insulating substrate. Hence, because the region with the strongest electrical field and the junction interface where avalanche is susceptible to occur overlap each other in the impurity profile as in the prior art, avalanche breakdown is very likely to occur. Even when off-set may be employed, the electrical field relaxation at the subbing interface is not so great.
The points as described in detail above are described in more detail by comparison with the prior art example.
For example, for relaxation of the electrical field in the vicinity of the drain edge, the method of Lightly-Doped-Drain (LDD) which forms a region with thin concentration in the vicinity of drain has been known in the art.
FIG. 2 is a cross-sectional view of the MOSFET of the thin film of the prior art created by use of the LDD method as mentioned above. In FIG. 2, 301 is a subbing insulating substrate, 302 a semiconductor layer, 303 a gate insulating film, 304 a polycrystalline silicon film, 309 a source, 310 a drain, 306 a low impurity concentration region source, and by forming the low impurity concentration region drain 307 in the vicinity of the drain 310, the high field in the vicinity of the drain 310 is attempted to be relaxed. In the same Figure, 308 is NSG, 311 PSG and 314, 315 are electrodes.
However, even in such an ultra-thin MOSFET, simultaneously with a deterioration of drain dielectric strength by the high field in the vicinity of the above-mentioned drain, if the film thickness of the semiconductor layer 302 is thinner than a certain film thickness, the drain dielectric strength when the gate voltage is 0 volt (during OFF) abruptly deteriorates as compared with the case of a thick film.
On the other hand, in the structure as shown in FIG. 2, in which the junction interface between the low impurity concentration region 307 of the drain and the high impurity concentration region 310 of the drain used in the prior art is located below the gate insulating film 303, the avalanche breakdown at the drain edge which determines the drain dielectric strength occurs generally in the vicinity of the polycrystalline silicon film 304 in the case of a thick film, while it occurs in the interface vicinity with the subbing insulating substrate 301 with a certain film thickness or less as described above.
As described in the above, in the prior art SOI type transistor, a problem concerned with withstand voltage remains.